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RF70
Low Power High Performance 2.4 GHz GFSK Transceiver
Features
2400-2483.5 MHz ISM band operation Support 1 and 2 Mbps air data rate Programmable output power (-40dBm to 5dBm) Low power consumption Tolerate +/- 60ppm 16 MHz crystal Variable payload length from 1 to 32bytes Automatic packet processing 6 data pipes for 1:6 star networks 1.9V to 3.6V power supply 4-pin SPI interface with maximum 8 MHz clock rate Compact 20-pin 4x4 mm QFN package and dice
V1.0
Pin Assignments
VSS 20 CDVDD 19 VDD 18 VSS 17 IREF 16
CE
1
15
VDD
CSN
2
14
VSS
SCK
3
RF70
13
RFN
MOSI
4
12
RFP
MISO
5
11
VDDPA
6 IRQ
7 VDD
8 VSS
9 XTALP
10 XTALN
Applications
Wireless PC peripherals Wireless mice and keyboards Wireless gamepads Wireless audio VOIP and wireless headsets Remote controls Consumer electronics Home automation Toys Personal health and entertainment
Block Diagram
RFP RFN
FM Demodulator
Rx FIFO Data Slicer
CSN SCK MOSI MISO IRQ CE
SPI Interface
Integrated TDD RF Transceiver
Power Management
Packet Processing & State Control
Register banks
FM Modulator
Gaussian shaping
Tx FIFO
XTALP
XTALN
RF70
Table of Contents
V1.0
General Description ................................................................................................................. 3 Abbreviations .......................................................................................................................... 4 Pin Information ....................................................................................................................... 5 State Control ........................................................................................................................... 6 4.1 State Control Diagram ............................................................................................................... 6 4.2 Power Down Mode.................................................................................................................... 7 4.3 Standby-I Mode ......................................................................................................................... 7 4.4 Standby-II Mode........................................................................................................................ 7 4.5 TX Mode ................................................................................................................................... 7 4.6 RX Mode ................................................................................................................................... 8 5 Packet Processing .................................................................................................................... 8 5.1 Packet Format ............................................................................................................................ 8 5.1.1 Preamble........................................................................................................................... 9 5.1.2 Address............................................................................................................................. 9 5.1.3 Packet Control .................................................................................................................. 9 5.1.4 Payload ........................................................................................................................... 10 5.1.5 CRC................................................................................................................................ 10 5.2 Packet Handling ...................................................................................................................... 10 6 Data and Control Interface .................................................................................................... 11 6.1 TX/RX FIFO ........................................................................................................................... 11 6.2 Interrupt ................................................................................................................................... 11 6.3 SPI Interface ............................................................................................................................ 12 6.3.1 SPI Command ................................................................................................................ 12 6.3.2 SPI Timing ..................................................................................................................... 13 7 Register Map ......................................................................................................................... 15 7.1 Register Bank 0 ....................................................................................................................... 15 7.2 Register Bank 1 ....................................................................................................................... 20 8 Electrical Specifications ......................................................................................................... 21 9 Typical Application Schematic ............................................................................................... 22 10 Package Information.............................................................................................................. 23 11 Order Information ................................................................................................................. 24 12 Contact Information .............................................................................................................. 25 1 2 3 4
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RF70
1
General Description
V1.0
RF70 is a GFSK transceiver operating in the world wide ISM frequency band at 24002483.5 MHz. Burst mode transmission and up to 2Mbps air data rate make them suitable for applications requiring ultra low power consumption. The embedded packet processing engines enable their full operation with a very simple MCU as a radio system. Auto re-transmission and auto acknowledge give reliable link without any MCU interference. RF70 operates in TDD mode, either as a transmitter or as a receiver. The RF channel frequency determines the center of the channel used by RF70. The frequency is set by the RF_CH register in register bank 0 according to the following formula: F0= 2400 + RF_CH (MHz). The
resolution of the RF channel frequency is 1MHz. A transmitter and a receiver must be programmed with the same RF channel frequency to be able to communicate with each other. The output power of RF70 is set by the RF_PWR bits in the RF_SETUP register. Demodulation is done with embedded data slicer and bit recovery logic. The air data rate can be programmed to 1Mbps or 2Mbps by RF_DR register. A transmitter and a receiver must be programmed with the same setting. In the following chapters, all registers are in register bank 0 except with explicit claim.
RFP RFN
FM Demodulator
Rx FIFO Data Slicer
CSN SCK MOSI MISO IRQ CE
SPI Interface
Integrated TDD RF Transceiver
Power Management
Packet Processing & State Control
Register banks
FM Modulator
Gaussian shaping
Tx FIFO
XTALP
XTALN
Figure 1 RF70 Chip Block Diagram
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RF70
2 Abbreviations
ACK ARC ARD CD CE CRC CSN DPL FIFO GFSK GHz LNA IRQ ISM LSB MAX_RT Mbps MCU MHz MISO MOSI MSB PA PID PLD PRX PTX PWD_DWN PWD_UP RF_CH RSSI RX RX_DR SCK SPI TDD TX TX_DS XTAL Acknowledgement Auto Retransmission Count Auto Retransmission Delay Carrier Detection Chip Enable Cyclic Redundancy Check Chip Select Not Dynamic Payload Length First-In-First-Out Gaussian Frequency Shift Keying Gigahertz Low Noise Amplifier Interrupt Request Industrial-Scientific-Medical Least Significant Bit Maximum Retransmit Megabit per second Microcontroller Unit Megahertz Master In Slave Out Master Out Slave In Most Significant Bit Power Amplifier Packet Identity Bits Payload Primary RX Primary TX Power Down Power Up Radio Frequency Channel Received Signal Strength Indicator Receive Receive Data Ready SPI Clock Serial Peripheral Interface Time Division Duplex Transmit Transmit Data Sent Crystal
V1.0
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RF70
3 Pin Information
VSS 20 CDVDD 19 VDD 18 VSS 17 IREF 16
V1.0
CE
1
15
VDD
CSN SCK
2
14
VSS RFN
3
RF70
13
MOSI
4
12
RFP
MISO
5
11
VDDPA
6 IRQ
7 VDD
8 VSS
9
10
XTALP XTALN
Figure 2 RF70 pin assignments (top view) for the QFN20 4x4 package
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Name
CE CSN SCK MOSI MISO IRQ VDD VSS XTALP XTALN VDDPA RFP RFN VSS VDD IREF VSS VDD CDVDD VSS
Pin Function
Digital Input Digital Input Digital Input Digital Input Digital Output Digital Output Power Ground Analog Output Analog Input Power RF port RF port Ground Power Analog Output Ground Power Analog Output Ground
Description
Chip Enable Activates RX or TX mode SPI Chip Select, Active low SPI Clock SPI Slave Data Input SPI Slave Data Output with tri-state option Maskable interrupt pin, Active low Power Supply (1.9 V to 3.6 V DC) Ground (0 V) Crystal oscillator, node P (inverter output) Crystal oscillator, node N (inverter input) 1.8V Regulator output for PA,TX:1.8V,RX:0V RF output (PA) /input (LNA), port P. RF output (PA) /Input (LNA), port N. Ground (0 V) Power Supply (1.9 V to 3.6 V DC) Reference current generation. A 22Kohm external resistor connected to ground. Ground (0 V) Power Supply (1.9 V to 3.6 V DC) Digital regulator output decoupling capacitor Ground (0 V)
Table 1 RF70 pin functions
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RF70
4 State Control
4.1

V1.0
State Control Diagram
Pin signal: VDD, CE SPI register: PWR_UP, PRIM_RX, EN_AA, NO_ACK, ARC, ARD System information: Time out, ACK received, ARD elapsed, ARC_CNT, TX FIFO empty, ACK packet transmitted, Packet received
VDD>=1.9 V
RF70 has built-in state machines that control the state transition between different modes. When auto acknowledge feature is disabled, state transition will be fully controlled by MCU.
Power Down
PWR_UP=1
PWR_UP=0
Standby-I
Time out or ACK received CE=1 ARD elapsed and ARC_CNTCE=0
TX FIFO empty
RX Standby-II
TX FIFO Data Ready
TX
EN_AA=1 NO_ACK=0
Figure 3 PTX (PRIM_RX=0) state control diagram
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RF70
VDD>=1.9 V
V1.0
Power Down
PWR_UP=1
PWR_UP=0
Standby-I
CE=1 CE=0 CE=0
ACK packet transmitted
RX
Packet received EN_AA=1 NO_ACK=0
TX
Figure 4 PRX (PRIM_RX=1) state control diagram
4.2
Power Down Mode
4.4
Standby-II Mode
In power down mode RF70 is in sleep mode with minimal current consumption. SPI interface is still active in this mode, and all register values are available by SPI. Power down mode is entered by setting the PWR_UP bit in the CONFIG register to low.
In standby-II mode more clock buffers are active than in standby-I mode and much more current is used. Standby-II occurs when CE is held high on a PTX device with empty TX FIFO. If a new packet is uploaded to the TX FIFO in this mode, the device will automatically enter TX mode and the packet is transmitted.
4.3
Standby-I Mode 4.5
By setting the PWR_UP bit in the CONFIG register to 1 and de-asserting CE to 0, the device enters standby-I mode. Standby-I mode is used to minimize average current consumption while maintaining short start-up time. In this mode, part of the crystal oscillator is active. This is also the mode which the RF70 returns to from TX or RX mode when CE is set low.
TX Mode
PTX device (PRIM_RX=0)
The TX mode is an active mode where the PTX device transmits a packet. To enter this mode from power down mode, the PTX device must have the PWR_UP bit set high, PRIM_RX bit set low, a payload in the TX FIFO, and a high pulse on the CE for more than 10s.
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RF70
The PTX device stays in TX mode until it finishes transmitting the current packet. If CE = 0 it returns to standby-I mode. If CE = 1, the next action is determined by the status of the TX FIFO. If the TX FIFO is not empty the PTX device remains in TX mode, transmitting the next packet. If the TX FIFO is empty the PTX device goes into standby-II mode. If the auto retransmit is enabled (EN_AA=1) and auto acknowledge is required (NO_ACK=0), the PTX device will enter TX mode from standby-I mode when ARD elapsed and number of retried is less than ARC. PRX device (PRIM_RX=1)
V1.0
set high. Or PRX device can enter this mode from TX mode after transmitting an acknowledge packet when EN_AA=1 and NO_ACK=0 in received packet. In this mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the packet processing engine. The packet processing engine continuously searches for a valid packet. If a valid packet is found (by a matching address and a valid CRC) the payload of the packet is presented in a vacant slot in the RX FIFO. If the RX FIFO is full, the received packet is discarded. The PRX device remains in RX mode until the MCU configures it to standby-I mode or power down mode. In RX mode a carrier detection (CD) signal is available. The CD is set to high when a RF signal is detected inside the receiving frequency channel. The internal CD signal is filtered before presented to CD register. The RF signal must be present for at least 128 s before the CD is set high. PTX device (PRIM_RX=0)
The PRX device will enter TX mode from RX mode only when EN_AA=1 and NO_ACK=0 in received packet to transmit acknowledge packet with pending payload in TX FIFO.
4.6
RX Mode
PRX device (PRIM_RX=1)
The RX mode is an active mode where the RF70 radio is configured to be a receiver. To enter this mode from standby-I mode, the PRX device must have the PWR_UP bit set high, PRIM_RX bit set high and the CE pin
The PTX device will enter RX mode from TX mode only when EN_AA=1 and NO_ACK=0 to receive acknowledge packet.
5 Packet Processing
5.1 Packet Format
The packet format has a preamble, address, packet control, payload and CRC field.
Preamble 1 byte
Address 3~5 byte
Packet Control 9/0 bit Payload 0~32 byte
CRC 2/1 byte
Payload Length 6 bit
PID 2 bit
NO_ACK 1 bit
Figure 5 Packet Format
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RF70
5.1.1 Preamble
V1.0
No other data pipe can receive data until a complete packet is received by a data pipe that has detected its address. When multiple PTX devices are transmitting to a PRX, the ARD can be used to skew the auto retransmission so that they only block each other once.
The preamble is a bit sequence used to detect 0 and 1 levels in the receiver. The preamble is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilize the receiver.
5.1.3
Packet Control
5.1.2
Address
When Dynamic Payload Length function is enabled, the packet control field contains a 6 bit payload length field, a 2 bit PID (Packet Identity) field and, a 1 bit NO_ACK flag. Payload length The payload length field is only used if the Dynamic Payload Length function is enabled. PID The 2 bit PID field is used to detect whether the received packet is new or retransmitted. PID prevents the PRX device from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI. The PID and CRC fields are used by the PRX device to determine whether a packet is old or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, RF70 compares the CRC sums from both packets. If the CRC sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. NO_ACK The NO_ACK flag is only used when the auto acknowledgement feature is used. Setting the flag high, tells the receiver that the packet is not to be auto acknowledged. The PTX can set the NO_ACK flag bit in the Packet Control Field with the command: W_TX_PAYLOAD_NOACK.However, the function must first be enabled in the FEATURE register by setting the EN_DYN_ACK bit. When you use this option,
This is the address for the receiver. An address ensures that the packet is detected by the target receiver. The address field can be configured to be 3, 4, or 5 bytes long by the AW register. The PRX device can open up to six data pipes to support up to six PTX devices with unique addresses. All six PTX device addresses are searched simultaneously. In PRX side, the data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. Each data pipe address is configured in the RX_ADDR_PX registers. Each pipe can have up to 5 bytes configurable address. Data pipe 0 has a unique 5 byte address. Data pipes 1-5 share the 4 most significant address bytes. The LSB byte must be unique for all 6 pipes. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. On the PRX the RX_ADDR_Pn, defined as the pipe address, must be unique. On the PTX the TX_ADDR must be the same as the RX_ADDR_P0 on the PTX, and as the pipe address for the designated pipe on the PRX.
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RF70
the PTX goes directly to standby-I mode after transmitting the packet and the PRX does not transmit an ACK packet when it receives the packet. 5.1.4 Payload 5.1.5 CRC
V1.0
The payload is the user defined content of the packet. It can be 0 to 32 bytes wide, and it is transmitted on-air as it is uploaded (unmodified) to the device. The RF70 provides two alternatives for handling payload lengths, static and dynamic payload length. The static payload length of each of six data pipes can be individually set. The default alternative is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. Static payload length is set by the RX_PW_Px registers. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal the value in the RX_PW_Px register on the receiver side. Each pipe has its own payload length. Dynamic Payload Length (DPL) is an alternative to static payload length. DPL enables the transmitter to send packets with variable payload length to the receiver. This means for a system with different payload lengths it is not necessary to scale the packet length to the longest payload. With DPL feature the RF70 can decode the payload length of the received packet automatically instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using the command: R_RX_PL_WID. In order to enable DPL the EN_DPL bit in the FEATURE register must be set. In RX mode the DYNPD register has to be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD set.
The CRC is the error detection mechanism in the packet. The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. It may be either 1 or 2 bytes and is calculated over the address, Packet Control Field, and Payload. The polynomial for 1 byte CRC is X8 + X2 + X + 1. Initial value is 0xFF. The polynomial for 2 byte CRC is X16 + X12 + X5 + 1. Initial value is 0xFFFF. No packet is accepted by receiver side if the CRC fails.
5.2
Packet Handling
for payload
RF70 uses burst mode transmission and receive.
The transmitter fetches payload from TX FIFO, automatically assembles it into packet and transmits the packet in a very short burst period with 1Mbps or 2Mbps air data rate. After transmission, if the PTX packet has the NO_ACK flag set, RF70 sets TX_DS and gives an active low interrupt IRQ to MCU. If the PTX is ACK packet, the PTX needs receive ACK from the PRX and then asserts the TX_DS IRQ. The receiver automatically validates and disassembles received packet, if there is a valid packet within the new payload, it will write the payload into RX FIFO, set RX_DR and give an active low interrupt IRQ to MCU. When auto acknowledge is enabled (EN_AA=1), the PTX device will automatically wait for acknowledge packet after transmission, and re-transmit original packet with the delay of ARD until an acknowledge packet is received or the number of re-transmission exceeds a threshold ARC. If the later one happens, RF70 will set MAX_RT and give an active low interrupt
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IRQ to MCU. Two packet loss counters (ARC_CNT and PLOS_CNT) are incremented each time a packet is lost. The ARC_CNT counts the number of retransmissions for the current transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. ARC_CNT is reset by initiating a new transaction. PLOS_CNT is reset by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The PTX device will retransmit if its RX FIFO is full but received ACK frame has payload. As an alternative for PTX device to auto retransmit it is possible to manually set the RF70 to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. When auto acknowledge is enabled, the PRX device will automatically check the NO_ACK field in received packet, and if NO_ACK=0, it will automatically send an acknowledge packet to PTX device. If EN_ACK_PAY is set, and the acknowledge packet can also include pending payload in TX FIFO.
V1.0
accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payload for ACK packets to three different PTX devices. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO by using the FLUSH_TX command. The RX FIFO in PRX may contain payload from up to three different PTX devices. . A TX FIFO in PTX can have up to three payloads stored. The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands give access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX mode. This command gives access to the RX_PLD register. The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted. In the FIFO_STATUS register it is possible to read if the TX and RX FIFO are full or empty. The TX_REUSE bit is also available in the FIFO_STATUS register. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI command: W_TX_PAYLOAD or FLUSH TX.
6 Data and Control Interface
6.1 TX/RX FIFO
The data FIFOs are used to store payload that is to be transmitted (TX FIFO) or payload that is received and ready to be clocked out (RX FIFO). The FIFO is accessible in both PTX mode and PRX mode. There are three levels 32 bytes FIFO for both TX and RX, supporting both acknowledge mode or no acknowledge mode with up to six pipes. TX three levels, 32 byte FIFO RX three levels, 32 byte FIFO
6.2
Interrupt
Both FIFOs have a controller and are
In RF70 there is an active low interrupt (IRQ) pin, which is activated when TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ are set high by the state machine in the STATUS register. The IRQ pin resets when MCU writes '1' to the IRQ source bit in the STATUS register. The IRQ mask in the CONFIG
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RF70
register is used to select the IRQ sources that are allowed to assert the IRQ pin. By setting one of the MASK bits high, the corresponding IRQ source is disabled. By default all IRQ sources are enabled. The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. If the STATUS register is read during an IRQ pin high to low transition, the pipe information is unreliable. to low transition on CSN.
V1.0
In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin. The serial shifting SPI commands is in the following format: for all registers at bank 0 and register 9 to register 14 at bank 1 for register 0 to register 8 at bank 1
6.3
6.3.1
SPI Interface
SPI Command
The SPI commands are shown in Table 2. Every new command must be started by a high
Command name
R_REGISTER W_REGISTER
Command word (binary)
000A AAAA 001A AAAA
# Data bytes
1 to 5 LSB byte first 1 to 5 LSB byte first 1 to 32 LSB byte first 1 to 32 LSB byte first 0 0
Operation
Read command and status registers. AAAAA = 5 bit Register Map Address Write command and status registers. AAAAA = 5 bit Register Map Address Executable in power down or standby modes only. Read RX-payload: 1 - 32 bytes. A read operation always starts at byte 0. Payload is deleted from FIFO after it is read. Used in RX mode. Write TX-payload: 1 - 32 bytes. A write operation always starts at byte 0 used in TX payload. Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. Used for a PTX device Reuse last transmitted payload. Packets are repeatedly retransmitted as long as CE is high. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission
R_RX_PAYLOAD
0110 0001
W_TX_PAYLOAD FLUSH_TX FLUSH_RX
1010 0000 1110 0001 1110 0010
REUSE_TX_PL
1110 0011
0
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V1.0
This write command followed by data 0x73 activates the following features: * R_RX_PL_WID * W_ACK_PAYLOAD * W_TX_PAYLOAD_NOACK A new ACTIVATE command with the same data deactivates them again. This is executable in power down or stand by modes only. ACTIVATE 0101 0000 1 The R_RX_PL_WID, W_ACK_PAYLOAD, and W_TX_PAYLOAD_NOACK features registers are initially in a deactivated state; a write has no effect, a read only results in zeros on MISO. To activate these registers, use the ACTIVATE command followed by data 0x73. Then they can be accessed as any other register. Use the same command and data to deactivate the registers again. This write command followed by data 0x53 toggles the register bank, and the current register bank number can be read out from REG7 [7] Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled using first in - first out principle. Write payload: 1- 32 bytes. A write operation always starts at byte 0. Used in TX mode. Disables AUTOACK on this specific packet. No Operation. Might be used to read the STATUS register
R_RX_PL_WID
0110 0000
W_ACK_PAYLOAD
1010 1PPP
1 to 32 LSB byte first
W_TX_PAYLOAD_NO ACK NOP
1011 0000 1111 1111
1 to 32 LSB byte first 0
Table 2 SPI command 6.3.2 SPI Timing
SCK CSN Write to SPI register: MOSI MISO
x C7 C6 C5 C4 C3 C2 C1 C0 x D7 D6 D5 D4 D3 D2 D1 D0 x
HI-Z
S7
S6
S5
S4
S3
S2
S1
S0
0
0
0
0
0
0
0
0
Hi-Z
Read from SPI register: MOSI MISO
x x C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 C0 S0 D7 D6 D5 D4 D3 x D2 D1 D0 x
Figure 6 SPI timing
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RF70
Cn: SPI command bit Sn: STATUS register bit Dn: Data Bit (LSB byte to MSB byte, MSB bit in each byte first)
V1.0
Note: The SPI timing is for bank 0 and register 9 to 14 at bank 1. For register 0 to 8 at bank 1, the byte order is inversed that the MSB byte is R/W before LSB byte.
Figure 7 SPI NOP timing diagram
Symbol
Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz
Parameters
Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z
Min
10 2
Max
Units
ns ns ns ns ns ns MHz ns ns ns ns ns
38 55 40 40 0 2 2 50 38
8 100
Table 3 SPI timing parameter
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7 Register Map
V1.0
There are two register banks, which can be toggled by SPI command "ACTIVATE" followed with 0x53 byte, and bank status can be read from Bank0_REG7 [7].
7.1
Register Bank 0
Reset Value
0 0
Address (Hex)
00
Mnemonic
CONFIG Reserved MASK_RX_DR
Bit
Type
Description
Configuration Register Only '0' allowed Mask interrupt caused by RX_DR 1: Interrupt not reflected on the IRQ pin 0: Reflect RX_DR as active low interrupt on the IRQ pin Mask interrupt caused by TX_DS 1: Interrupt not reflected on the IRQ pin 0: Reflect TX_DS as active low interrupt on the IRQ pin Mask interrupt caused by MAX_RT 1: Interrupt not reflected on the IRQ pin 0: Reflect MAX_RT as active low interrupt on the IRQ pin Enable CRC. Forced high if one of the bits in the EN_AA is high CRC encoding scheme '0' - 1 byte '1' - 2 bytes 1: POWER UP, 0:POWER DOWN RX/TX control, 1: PRX, 0: PTX Enable Auto Acknowledgment Function
7 6
R/W R/W
MASK_TX_DS
5
0
R/W
MASK_MAX_RT
4
0
R/W
EN_CRC CRCO
3 2
1 0
R/W R/W
PWR_UP PRIM_RX
1 0
0 0
R/W R/W
01
EN_AA Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 7:6 5 4 3 2 1 0 00 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W
Only '00' allowed Enable auto acknowledgement data pipe 5 Enable auto acknowledgement data pipe 4 Enable auto acknowledgement data pipe 3 Enable auto acknowledgement data pipe 2 Enable auto acknowledgement data pipe 1 Enable auto acknowledgement data pipe 0 Enabled RX Addresses Only '00' allowed Enable data pipe 5. Enable data pipe 4. Enable data pipe 3. Enable data pipe 2. Enable data pipe 1. Enable data pipe 0.
02
EN_RXADDR Reserved ERX_P5 ERX_P4 ERX_P3 ERX_P2 ERX_P1 ERX_P0
7:6 5 4 3 2 1 0
00 0 0 0 0 1 1
R/W R/W R/W R/W R/W R/W R/W
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RF70
03 SETUP_AW Reserved AW 7:2 1:0 000000 11 R/W R/W Setup of Address Widths (common for all data pipes) Only '000000' allowed RX/TX Address field width '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' - 5 bytes LSB bytes are used if address width is below 5 bytes
V1.0
04
SETUP_RETR ARD
7:4
0000
R/W
ARC
3:0
0011
R/W
Setup of Automatic Retransmission Auto Retransmission Delay 0000 - Wait 250 us 0001 - Wait 500 us 0010 - Wait 750 us ........ 1111 - Wait 4000 us (Delay defined from end of transmission to start of next transmission) Auto Retransmission Count 0000 -Re-Transmit disabled 0001 - Up to 1 Re-Transmission on fail of AA ...... 1111 - Up to 15 Re-Transmission on fail of AA RF Channel Only '0' allowed Sets the frequency channel RF Setup Register Reserved Reserved Reserved Reserved Air Data Rate 0 - 1Mbps 1 - 2Mbps Set RF output power in TX mode RF_PWR[1:0] '00' - -10 dBm '01' - -5 dBm '10' - 0 dBm '11' - 5 dBm Setup LNA gain 0:Low gain(20dB down) 1:High gain Status Register (In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) Register bank selection states. Switch register bank is done by SPI command "ACTIVATE" followed by 0x53 0: Register bank 0
05
RF_CH Reserved RF_CH RF_SETUP Reserved
7 6:0
0 0000010
R/W R/W
06
RF_DR
7 6 5 4 3
0 0 1 1 1
R/W R/W R/W R/W
RF_PWR[1:0]
2:1
11
R/W
LNA_HCURR
0
1
R/W
07
STATUS
RBANK
7
0
R
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RF70
RX_DR 6 0 R/W
V1.0
TX_DS
5
0
R/W
MAX_RT
4
0
R/W
RX_P_NO
3:1
111
R
TX_FULL
0
0
R
1: Register bank 1 Data Ready RX FIFO interrupt Asserted when new data arrives RX FIFO Write 1 to clear bit. Data Sent TX FIFO interrupt Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. Maximum number of TX retransmits interrupt Write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable further communication. Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not used 111: RX FIFO Empty TX FIFO full flag. 1: TX FIFO full 0: Available locations in TX FIFO Transmit observe register Count lost packets. The counter is overflow protected to 15, and discontinues at max until reset. The counter is reset by writing to RF_CH. Count retransmitted packets. The counter is reset when transmission of a new packet starts.
08
OBSERVE_TX PLOS_CNT 7:4 0000 R
ARC_CNT
3:0
0000
R
09
CD Reserved CD RX_ADDR_P0
7:1 0 39:0
000000 0 0xE7E7E 7E7E7
R R R/W
Carrier Detect Receive address data pipe 0. 5 Bytes maximum length. (LSB byte is written first. Write the number of bytes defined by SETUP_AW) Receive address data pipe 1. 5 Bytes maximum length. (LSB byte is written first. Write the number of bytes defined by SETUP_AW) Receive address data pipe 2. Only LSB MSB bytes is equal to RX_ADDR_P1[39:8] Receive address data pipe 3. Only LSB MSB bytes is equal to RX_ADDR_P1[39:8] Receive address data pipe 4. Only LSB. MSB bytes is equal to RX_ADDR_P1[39:8] Receive address data pipe 5. Only LSB. MSB bytes is equal to RX_ADDR_P1[39:8] Transmit address. Used for a PTX device only. (LSB byte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX device
0A
0B
RX_ADDR_P1
39:0
0xC2C2C 2C2C2 0xC3 0xC4 0xC5 0xC6
R/W
0C 0D 0E 0F
RX_ADDR_P2 RX_ADDR_P3 RX_ADDR_P4 RX_ADDR_P5
7:0 7:0 7:0 7:0
R/W R/W R/W R/W
10
TX_ADDR
39:0
0xE7E7E 7E7E7
R/W
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RF70
11 RX_PW_P0 Reserved 7:6 00 R/W
V1.0
RX_PW_P0
5:0
000000
R/W
Only '00' allowed Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes
12
RX_PW_P1 Reserved RX_PW_P1
7:6 5:0
00
R/W
000000
R/W
Only '00' allowed Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes
13
RX_PW_P2 Reserved RX_PW_P2
7:6 5:0
00 000000
R/W R/W
Only '00' allowed Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes
14
RX_PW_P3 Reserved
7:6 5:0
00 000000
R/W
RX_PW_P3
R/W
Only '00' allowed Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes
15
RX_PW_P4 Reserved
7:6
00
R/W
RX_PW_P4
5:0
000000
R/W
Only '00' allowed Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes
16
RX_PW_P5 Reserved RX_PW_P5
7:6
00 000000
R/W
5:0
R/W
Only '00' allowed Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0: not used 1 = 1 byte ... 32 = 32 bytes FIFO Status Register Only '0' allowed Reuse last transmitted data packet if set high.
17
FIFO_STATUS Reserved TX_REUSE
7 6
0 0
R/W R
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RF70
V1.0
TX_FULL
5
0
R
TX_EMPTY Reserved RX_FULL
4 3:2 1
1 00 0
R R/W R
RX_EMPTY N/A ACK_PLD
0 255:0
1 X
R W
N/A
TX_PLD
255:0
X
W
N/A
RX_PLD
255:0
X
R
The packet is repeatedly retransmitted as long as CE is high. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI command W_TX_PAYLOAD or FLUSH TX TX FIFO full flag 1: TX FIFO full; 0: Available locations in TX FIFO TX FIFO empty flag. 1: TX FIFO empty 0: Data in TX FIFO Only '00' allowed RX FIFO full flag 1: RX FIFO full 0: Available locations in RX FIFO RX FIFO empty flag 1: RX FIFO empty 0: Data in RX FIFO Written by separate SPI command ACK packet payload to data pipe number PPP given in SPI command Used in RX mode only Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled first in first out. Written by separate SPI command TX data pay-load register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only Read by separate SPI command RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX channels share the same FIFO. Enable dynamic payload length Only 00 allowed Enable dynamic payload length data pipe 5. (Requires EN_DPL and ENAA_P5) Enable dynamic payload length data pipe 4. (Requires EN_DPL and ENAA_P4) Enable dynamic payload length data pipe 3. (Requires EN_DPL and ENAA_P3) Enable dynamic payload length data pipe 2. (Requires EN_DPL and ENAA_P2) Enable dynamic payload length data pipe 1. (Requires EN_DPL and ENAA_P1) Enable dynamic payload length data pipe 0. (Requires EN_DPL and ENAA_P0) Feature Register Only 00000 allowed Enables Dynamic Payload Length Enables Payload with ACK Enables the W_TX_PAYLOAD_NOACK command
1C
DYNPD Reserved DPL_P5 DPL_P4 DPL_P3 DPL_P2 DPL_P1 DPL_P0
7:6 5 4 3 2 1 0
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
1D
FEATURE Reserved EN_DPL EN_ACK_PAY EN_DYN_ACK
7:3 2 1 0
0 0 0 0
R/W R/W R/W R/W R/W
Note: Don't write reserved registers and registers at other addresses in register bank 0 Table 4 Register Bank 0
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RF70
7.2 Register Bank 1
Mnemonic Bit
31:0 31:0 31:0 31:0 31:0
V1.0
Address (Hex)
00 01 02 03 04
Reset Value
0 0 0 0x 03001200 0
Type
W W W W W
Description
Must write with 0x404B01E2 Must write with 0xC04B0000 Must write with 0xD0FC8C02 Must write with 0x99003941 Must write with 0xD99E860B(High Power) For single carrier mode:0xD99E8621 RF output power in TX mode: 0:Low power(-30dB down) 1:High power Must write with 0x24067FA6(Disable RSSI) RSSI Threshold for CD detect 0: -97 dBm, 2 dB/step, 15: -67 dBm RSSI measurement: 0:Enable 1:Disable Reserved Reserved Register bank selection states. Switch register bank is done by SPI command "ACTIVATE" followed by 0x53 0: Register bank 0 1: Register bank 1 BEKEN Chip ID: 0x00000063(RF70) Reserved Reserved Reserved Please initialize with 0x00731200 Please initialize with 0x0080B436 Ramp curve Please write with 0xFFFFFEF7CF208104082041
20 05 RSSI_TH 31:0 29:26
1 0
W W W
RSSI_EN 06 07
18 31:0 31:0
0 0 0
W W W
RBANK 08 09 0A 0B 0C 0D Chip ID
7 31:0 0 0 0 0 0 0 NA
R R
0E
NEW_FEATURE RAMP
31:0 31:0 87:0
W
Note: Don't write reserved registers and no definition registers in register bank 1 Table 5 Register Bank 1
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RF70
8 Electrical Specifications
Name
VDD TEMP VIH VIL VOH VOL IVDD IVDD IVDD FOP FXTAL RFSK PRF PBW PBW PRF1 PRF2 IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD IVDD Max Input RXSENS RXSENS C/ICO C/I1ST C/I2ND C/I3RD C/ICO C/I1ST C/I2ND C/I3RD
V1.0
Parameter (Condition)
Operating Condition Voltage Temperature Digital input Pin High level Low level Digital output Pin High level (IOH=-0.25mA) Low level(IOL=0.25mA) Normal condition Power Down current Standby-I current Standby-II current Normal RF condition Operating frequency Crystal frequency Air data rate Transmitter Output power Modulation 20 dB bandwidth(2Mbps) Modulation 20 dB bandwidth (1Mbps) Out of band emission 2 MHz Out of band emission 4 MHz Current at -40 dBm output power Current at -30 dBm output power Current at -25 dBm output power Current at -10 dBm output power Current at -5 dBm output power Current at 0 dBm output power Current at 5 dBm output power Receiver Current (2Mbps) Current (1Mbps) 1 E-3 BER 1 E-3 BER sensitivity (2Mbps) 1 E-3 BER sensitivity (1Mbps) Co-channel C/I (2Mbps) ACS C/I 2MHz (2Mbps) ACS C/I 4MHz (2Mbps) ACS C/I 6MHz (2Mbps) Co-channel C/I (1Mbps) ACS C/I 1MHz (1Mbps) ACS C/I 2MHz (1Mbps) ACS C/I 3MHz (1Mbps)
Min
1.9 -40 0.7VDD VSS VDD- 0.3 0
Typi cal
3.0 +27
Max
3.6 +85 5.25 0.3VDD VDD 0.3 3 50 400
Unit
V C V V V V uA uA uA MHz MHz Mbps dBm MHz MHz dBm dBm mA mA mA mA mA mA mA mA mA dBm dBm dBm dB dB dB dB dB dB dB dB
Comm ent
2400 16 1 -40 0 2.5 1.3 -20 -40 11 11 12 13 15 17 23 18 17 10 -85 -88 4 -5 -20 -25 4 4 -18 -19
2527 2 5
Table 6 Electrical Specifications
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RF70
9 Typical Application Schematic
V1.0
Figure 8 RF70 typical application schematic
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RF70
10 Package Information
RF70 uses the QFN20 4x4 package, with matt tin plating.
V1.0
Parameter A A1 A3 D E B L D2 E2 E
Min 0.70 0.00 3.95 3.95 0.18 0.30 2.55 2.55
Typ 0.75 0.20 REF 4.00 4.00 0.23 0.40 2.70 2.70 0.50 REF
Max 0.80 0.05 4.05 4.05 0.30 0.50 2.80 2.80
Unit mm mm mm mm mm mm mm mm mm mm
Figure 9 QFN4*4 20 Pin package diagram
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RF70
11 Order Information
V1.0
Part number RF70 RF70-DICE
Package QFN DICE
Packing Tape Reel
Table 7 RF70 order information
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RF70
12 Contact Information
V1.0
This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no HOPE MICROELECTRONICS CO.,LTD 4/F, Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China Tel: 86-755-86096602 Fax: 86-755-86096587 Email: sales@hoperf.com Website: http://www.hoperf.com http://www.hoperf.cn http://hoperf.en.alibaba.com responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
(c)2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.
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